ISD S.A. is seeking to employ an ASIC Design Engineer for digital and/or mixed-signal SoC development in deep sub-micron silicon technologies.
- BS or MS in Computer Science, Electrical/Electronic Engineering, Software Engineering or related field
- Very good written and spoken English language
- Full RTL to GDSII flow, from synthesis to placement.
- Equivalence checking and Static Timing Analysis.
- DFT (ATPG, Scan Insertion).
- Floor planning.
- Synopsys Design Compiler for logic synthesis
- Cadence Encounter Digital Implementation System for place and route.