PLL200RH: low jitter CMOS PLL synthesizer clock synchronizer


PLL200RH is a low-jitter, PLL based multi-phase output clock generator and synchronizer IP functional block. The integrated VCO architecture can generate a stable CMOS output clock signal in excess of 200 MHz, which is locked in phase to an externally provided reference clock of a much lower frequency. Thanks to a set of clock dividers in both the feed-forward and feed-back clock signal paths, the output frequency is programmable through a set of dedicated CMOS pins. Thanks to the quad phase internal PLL architecture, the phase of the clock output can be set to 90° steps out of phase to the reference clock. By replicating the output stage, it is possible to form a multiple clock output clock synchronizer circuit that allows the synchronous distribution of the common clock signal to multiple receivers at different output phases.


  • Low jitter quad phase PLL core
  • Single 3.3V ± 10% power supply domain
  • Output frequency range 25MHz to > 200MHz
  • Output clock interface 2.5V or 3.3V LVCMOS
  • PLL lock output flag
  • Selectable edge synchronization to the reference clock
  • Power down input
  • Configurable frequency dividers
  • Crystal oscillator reference input
  • Output phase adjustment at 90° steps
  • Can drive capacitive loads to 10pF
  • Input reference clock input to 50MHz
  • Phase noise < -100dBc/Hz @ 1kHz offset
  • Power consumption < 350mW
  • TID tolerant to 100 krad (Si)
  • SEL immune to LET of 67 MeV-cm2/mg
  • SEU immune to LET of 67 MeV-cm2/mg
  • Extended ambient operating temperature range: -55°C to +125°C
  • Flight heritage available


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